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NB6VQ572M 1.8V / 2.5V Differential 4:1 Mux w/Input Equalizer to 1:2 CML Clock/Data Fanout / Translator
Multi-Level Inputs w/ Internal Termination
Description
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The NB6VQ572M is a high performance differential 4:1 Clock / Data input multiplexer and a 1:2 CML Clock / Data fanout buffer that operates up to 5 GHz / 6.5 Gbps respectively with a 1.8 V or 2.5 V power supply. Each INx / INx input pair incorporates a fixed Equalizer Receiver, which when placed in series with a Clock / Data path, will enhance the degraded signal transmitted across an FR4 backplane or cable interconnect. For applications that do not require Equalization, consider the NB7V572M, which is pin-compatible to the NB6VQ572M. The differential Clock / Data inputs have internal 50 W termination resistors and will accept differential LVPECL, CML, or LVDS logic levels. The NB6VQ572M incorporates a pair of Select pins that will choose one of four differential inputs and will produce two identical CML output copies of Clock or Data. As such, the NB6VQ572M is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock/Data distribution applications. The two differential CML outputs will swing 400 mV when externally loaded and terminated with a 50 W resistor to VCC and are optimized for low skew and minimal jitter. The NB6VQ572M is offered in a low profile 5x5 mm 32-pin QFN Pb-Free package. Application notes, models, and support documentation are available at www.onsemi.com. The NB6VQ572M is a member of the ECLinPS MAXTM family of high performance clock products.
Features
1
32
QFN32 MN SUFFIX CASE 488AM
NB6V Q572M AWLYYWWG G
A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 10 of this data sheet.
* * * * * * * *
Input Data Rate > 6.5 Gb/s Typical Data Dependent Jitter < 10 ps Maximum Input Clock Frequency > 5 GHz Typical Random Clock Jitter < 0.8 ps RMS Low Skew 1:2 CML Outputs, < 15 ps max 4:1 Multi-Level Mux Inputs, accepts LVPECL, CML, LVDS 175 ps Typical Propagation Delay 45 ps Typical Rise and Fall Times
* Differential CML Outputs, 400 mV Peak-to-Peak, * * * * * *
Typical Operating Range: VCC = 1.71 V to 2.625 V with GND =0V Internal 50 W Input Termination Resistors VREFAC Reference Output QFN-32 Package, 5mm x 5mm, Pb-Free -40C to +85C Ambient Operating Temperature These are Pb-Free Devices
(c) Semiconductor Components Industries, LLC, 2009
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April, 2009 - Rev. 0
Publication Order Number: NB6VQ572M/D
NB6VQ572M
Multilevel Inputs LVPECL, LVDS, CML IN0 VT0 IN0 50 W 50 W
EQ0
0
VREFAC0 IN1 VT1 IN1 50 W 50 W
CML OUTPUTS Q0 EQ1 1 4:1 MUX Q0
VREFAC1 IN2 VT2 IN2 50 W 50 W
EQ2
2
Q1 Q1
VREFAC2 IN3 VT3 IN3 50 W 50 W
EQ3
3
VREFAC3 SEL0 SEL1
Figure 1. Simplified Block Diagram
VREFAC3
VREFAC2
VT3
VT2
IN3
IN3
IN2
IN2
Exposed Pad (EP)
Table 1. INPUT SELECT FUNCTION TABLE
SEL1* 0 SEL0* 0 1 0 1 Clock / Data Input Selected IN0 Input Selected IN1 Input Selected IN2 Input Selected IN3 Input Selected
32 IN0 VT0 VREFAC0 IN0 IN1 VT1 VREFAC1 IN1 1 2 3 4 5 6 7 8 9 GND
31
30
29
28
27
26
25 24 23 22 GND VCC Q1 Q1 VCC NC SEL1 VCC
0 1 1
NB6VQ572M
21 20 19 18 17
*Defaults HIGH when left open.
10 VCC
11 Q0
12 Q0
13 VCC
14 NC
15 SEL0
16 VCC
Figure 2. Pinout: QFN-32 (Top View)
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NB6VQ572M
Table 2. PIN DESCRIPTION
Pin Number 1, 4 5, 8 25, 28 29, 32 2, 6 26, 30 15 18 14, 19 10, 13, 16 17, 20, 23 11, 12 21, 22 9, 24 3 7 27 31 - Pin Name IN0, IN0 IN1, IN1 IN2, IN2 IN3, IN3 VT0, VT1 VT2, VT3 SEL0 SEL1 NC VCC Q0, Q0 Q1, Q1 GND VREFAC0 VREFAC1 VREFAC2 VREFAC3 EP - LVTTL/LVCMOS Input - - CML Output I/O LVPECL, CML, LVDS Input Pin Description Noninverted, Inverted, Differential Clock or Data Inputs
Internal 100 W Center-tapped Termination Pin for INx / INx Input Select pins, default HIGH when left open through a 94 kW pullup resistor. Input logic threshold is VCC/2. See Select Function, Table 1. No Connect Positive Supply Voltage. Inverted, Non-inverted Differential Outputs. Negative Supply Voltage Output Voltage Reference for Capacitor-Coupled Inputs
-
The Exposed Pad (EP) on the QFN-32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat-sinking conduit. The pad is electrically connected to the die, and must be electrically connected to GND.
1. In the differential configuration when the input termination pins (VT0, VT1, VT2, VT3) are connected to a common termination voltage or left open, and if no signal is applied on INx/INx input, then the device will be susceptible to self-oscillation. 2. All VCC, and GND pins must be externally connected to a power supply for proper operation.
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NB6VQ572M
Table 3. ATTRIBUTES
Characteristics ESD Protection RPU - SELx Input Pullup Resistor Moisture Sensitivity (Note 3) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. QFN-32 Oxygen Index: 28 to 34 Human Body Model Machine Model Value > 2 kV > 200 V 94kW Level 1 UL 94 V-0 @ 0.125 in 221
Table 4. MAXIMUM RATINGS
Symbol VCC VIN VINPP Iout IIN IVREFAC TA Tstg qJA qJC Tsol Parameter Positive Power Supply Positive Input Voltage Differential Input Voltage |IN - IN| Output Current Through RT (50 W Resistor) Input current Through RT (50 W Resistor) VREFAC Sink or Source Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 4) Thermal Resistance (Junction-to-Case) (Note 4) Wave Solder v 20 sec 0 lfpm 500 lfpm QFN-32 QFN-32 QFN-32 Condition 1 GND = 0 V GND = 0 V Condition 2 Rating 3.0 -0.5 to VCC +0.5 1.89 $40 $40 $1.5 -40 to +85 -65 to +150 31 27 12 265 Unit V V V mA mA mA C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB6VQ572M
Table 5. DC CHARACTERISTICS CML OUTPUT VCC = 1.71 V to 2.625 V , GND = 0 V, TA = -40C to +85C (Note 5)
Symbol POWER SUPPLY VCC ICC Power Supply Voltage Power Supply Current for VCC (Inputs and Outputs Open) VCC = 2.5 V VCC = 1.8 V VCC = 2.5 V VCC = 1.8 V 2.375 1.71 70 60 2.5 1.8 105 85 2.625 1.89 140 120 V mA Characteristic Min Typ Max Unit
CML OUTPUTS (Note 6) VOH Output HIGH Voltage VCC = 2.5 V VCC = 1.8 V VCC = 2.5 V VCC =1.8 V VCC - 30 2470 1770 VCC - 550 1950 1250 VCC - 10 2490 1790 VCC - 450 2050 1350 VCC 2500 1800 VCC - 350 2150 1450 mV
VOL
Output LOW Voltage
mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED (Figures 7 and 8) (Note 7) VIH VIL Vth VISE VREFAC VREFAC VIHD VILD VID VCMR IIH IIL VIH VIL IIH IIL RTIN RTOUT Output Reference Voltage (100 mA Load) VCC - 700 1200 0 100 1150 -150 -150 VCC - 550 VCC - 450 VCC VIHD - 100 1200 VCC - 50 150 150 mV Single-ended Input HIGH Voltage Single-ended Input LOW Voltage Input Threshold Reference Voltage Range (Note 8) Single-ended Input Voltage (VIH - VIL) Vth + 100 GND 1100 200 VCC Vth - 100 VCC - 100 1200 mV mV mV mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 9 and 10) (Note 9) Differential Input HIGH Voltage (IN, IN) Differential Input LOW Voltage (IN, IN) Differential Input Voltage (IN, IN) (VIHD - VILD) Input Common Mode Range (Differential Configuration, Note 10) (Figure 11) Input HIGH Current IN / IN (VTIN/VTIN Open) Input LOW Current IN / IN (VTIN/VTIN Open) mV mV mV mV mA mA V V mA mA
CONTROL INPUT (SELx Pin) Input HIGH Voltage for Control Pin Input LOW Voltage for Control Pin Input HIGH Current Input LOW Current VCC x 0.65 GND -150 -150 VCC VCC x 0.35 150 150
TERMINATION RESISTORS Internal Input Termination Resistor (Measured from INx to VTx) Internal Output Termination Resistor 45 45 50 50 55 55 W W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and Output parameters vary 1:1 with VCC. 6. CML outputs loaded with 50 W to VCC for proper operation. 7. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously. 8. Vth is applied to the complementary input when operating in single-ended mode. 9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal.
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NB6VQ572M
Table 6. AC CHARACTERISTICS VCC = 1.71 V to 2.625 V, GND = 0 V, TA = -40C to +85C (Note 11)
Symbol fMAX fDATAMAX fSEL VOUTPP tPLH, tPHL tPD Tempco tskew tDC FN Characteristic Maximum Input Clock Frequency Maximum Operating Data Rate Maximum Toggle Frequency, SELx Output Voltage Amplitude (@ VINPPmin) (Note 12) (Figure 12) fin 5 GHz Propagation Delay to Differential Outputs Measured at Differential Crosspoint @ 1 GHz INx/INx to Qx/Qx @ 50 MHz SELx to Qx VOUT w 250 mV NRZ, (PRBS23) Min 5 6.5 4 250 100 Typ 6 8 10 400 175 7 50 0 30 fIN v 5 GHz 10 kHz 100 kHz 1 MHz 10 MHz 20 MHz 40 MHz 45 50 -135 -136 -149 -150 -150 -151 35 0.2 0.8 10 0.7 100 25 45 1200 65 15 100 55 250 20 Max Unit GHz Gbps MHz mV ps ns Dfs/C ps % dBc
Differential Propagation Delay Temperature Coefficient Output - Output skew (within device) (Note 13) Device - Device skew (tpdmax - tpdmin) Output Clock Duty Cycle (Reference Duty Cycle = 50%) Phase Noise, fin = 1 GHz
t FN tJITTER
Integrated Phase Jitter (Figure TBD) fin = 1 GHz, 12 kHz - 20 MHz Offset (RMS) Random Clock Jitter, RJ (Note 14) Deterministic Jitter, DJ (Note 15) fin 5 GHz fin 6.5 Gbps (12" FR4)
fs ps RMS ps pk-pk ps RMS mV ps
Crosstalk Induced Jitter (Adjacent Channel) (Note 17) VINPP tr,, tf Input Voltage Swing (Differential Configuration) (Note 16) Output Rise/Falltimes @ 1 GHz; (20% - 80%), VIN = 400 mV Qx, Qx
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Measured using a 100 mVpk-pk source, 50% duty cycle clock source. All output loading with external 50 W to VCC. Input edge rates 40 ps (20% - 80%). 12. Output voltage swing is a single-ended measurement operating in differential mode. 13. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when the delays are measured from crosspoint of the inputs to the crosspoint of the outputs. 14. Additive RMS jitter with 50% duty cycle clock signal. 15. Additive Peak-to-Peak data dependent jitter with input NRZ data at PRBS23. 16. Input voltage swing is a single-ended measurement operating in differential mode. 17. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the inputs.
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NB6VQ572M
600 OUTPUT VOLTAGE AMPLITUDE (mV) 500 400 300 200 100 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 fin, CLOCK INPUT FREQUENCY (GHz) 8.0
Q AMP (mV)
Figure 3. Clock Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typical)
600 500 EYE HEIGHT (mV) 400 300 200 100 0
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
fDATA, DATA RATE (Gbps) Figure 4. Inside Eye Height vs. Input Data Rate (Gbps) at Ambient Temperature (typical), FR4 = 12"
VTx Driver Q FR4 - 12 Inch Backplane INx
NB6VQ572M
Q
INx
DJ1
DJ2
DJ3
Figure 5. Typical NB6VQ572M Equalizer Application and Interconnect with PRBS23 Pattern at 6.5 Gbps
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NB6VQ572M
VCC
VIH Vth INx 50 W VTx 50 W INx VIL
IN
Vth
IN
Figure 7. Differential Input Driven Single-Ended Figure 6. Input Structure
VCC Vthmax
VIHmax VILmax IN VIH Vth VIL VIHmin VILmin IN
Vth Vthmin VEE
IN
Figure 8. Vth Diagram
Figure 9. Differential Inputs Driven Differentially
VCC VCMmax VID = |VIHD(IN) - VILD(IN)| VIHD VILD VCMmin IN VCMR IN
VIHDmax VILDmax VIHDtyp VILDtyp VIHDmin VILDmin
VID = VIHD - VILD
IN IN
VEE
Figure 10. Differential Inputs Driven Differentially
Figure 11. VCMR Diagram
IN VINPP = VIH(IN) - VIL(IN) IN Q VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH Qx Qx SELx
VCC / 2
VCC / 2
tpd
tpd
Figure 12. AC Reference Measurement
Figure 13. SELx to Qx Timing Diagram
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NB6VQ572M
VCC VCC VCC VCC
Zo = 50 W LVPECL Driver VT = GND
NB6VQ572M IN 50 W 50 W LVDS Driver
Zo = 50 W VT = OPEN
NB6VQ572M IN 50 W 50 W
Zo = 50 W CLKx GND
IN
Zo = 50 W CLKx GND GND
IN
GND
Figure 14. LVPECL Interface
Figure 15. LVDS Interface
VCC
VCC
VCC
VCC
Zo = 50 W CML Driver VT = VCC
NB6VQ572M IN 50 W 50 W Differential Driver
Zo = 50 W VT = VREFAC*
NB6VQ572M IN 50 W 50 W
Zo = 50 W
IN
Zo = 50 W
IN
GND
GND
GND
GND
Figure 16. Standard 50 W Load CML Interface
Figure 17. Capacitor-Coupled Differential Interface (VT Connected to VREFAC)
*VREFAC bypassed to ground with a 0.01 mF capacitor.
NB6VQ572M VCC
RECEIVER VCC (Receiver)
50 W
50 W
Q Q
50 W
50 W
16 mA GND
Figure 18. Typical CML Output Structure and Termination
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NB6VQ572M
DEVICE ORDERING INFORMATION
Device NB6VQ572MMNG NB6VQ572MMNR4G Package QFN-32 (Pb-free) QFN-32 (Pb-free) Shipping 74 Units / Rail 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NB6VQ572M
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P CASE 488AM-01 ISSUE O
D
A B
2X 2X
0.15 C 0.15 C 0.10 C
32 X
0.08 C L
32 X
32 X b 0.10 C A B
0.05 C BOTTOM VIEW 0.28
32 X 28 X
ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
EE EE
TOP VIEW SIDE VIEW
9 8
PIN ONE LOCATION
E
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 --- --- 0.300 0.400 0.500
(A3) A A1 C
EXPOSED PAD 16 SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
SOLDERING FOOTPRINT*
5.30 3.20
D2
K
17 32 X
E2
1 32 25 24
0.63
32 X
e
3.20
5.30
0.50 PITCH
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NB6VQ572M/D

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